This invention relates to improved methods and systems for the metallization of semiconductor devices such as integrated circuits, memory cells, and the like that use copper metallization; more specifically this invention relates to methods and systems for copper-based metallization of silicon integrated circuits.
An important part of the fabrication of semiconductor devices is the metallization of the devices to electrically interconnect the device elements. For many such devices, the metallization of choice includes the use of copper metal lines. Metallization systems that use copper metal lines also must use a barrier material to isolate the copper from copper sensitive areas of the electronic devices. Some of the commonly used barrier layers for copper metallization are materials such as tantalum, such as tantalum nitride, and such as combined layers of tantalum and tantalum nitride.
The usual fabrication process for metallization systems that use copper involves the deposition of copper onto the barrier layers. Typically, a seed layer of copper is deposited onto the barrier layer; the seed layer of copper is then followed by a copper gapfill layer which provides the bulk copper for filling trenches and vias for the metallization. A preferred process for depositing the copper gapfill is electrochemical plating which typically uses a seed layer of copper.
One problem that occurs in the standard technology used for copper metallization is that many of the preferred barrier materials such as tantalum and tantalum nitride, if exposed to air for extended periods of time, can form oxides such as tantalum oxide and tantalum oxynitride on the surface of the barrier layer. It is known that electroless deposition of copper onto the barrier layer for use as a seed layer is inhibited if there is oxide present on the barrier layer. In addition, copper does not adhere to the oxide on the barrier layer as well as it adheres to the pure barrier metal or metal rich barrier layer surface, such as tantalum and tantalum-rich surface on tantalum nitride.
Another problem that occurs for the standard technology is that the requirements for new device technologies include using thinner copper layers as seed layers. These seed layers are often deposited by a physical vapor deposition process which has poor step coverage and produces an overhang for trenches and vias that can significantly narrow the opening of vias and trenches. Each of these problems can contribute to degrading the quality of electroplated gapfill copper. The overhang produced by deposition of copper by physical vapor deposition can cause pinch off for the electroplated copper, possibly leaving a liquid filled void in the gapfill copper. The requirements for a thinner copper layer for the seed layer may result in very thin copper layers on the sidewalls of features to be coated. The copper layer may even be discontinuous along the sidewall and can further contribute to formation of voids in the gapfill copper. The poor quality copper gapfill that may result from the new requirements for seed layers can have a significant impact on the reliability of the electronic devices using such copper metallization systems.
Clearly, there are numerous applications requiring high-performance, high reliability electronic devices. The problems that occur for the standard technology for fabricating electronic devices using copper metallization indicate there is a need for methods and structures that can allow the fabrication of electronic devices using copper metallization with improved performance and improved reliability. More specifically, there is a need for copper metallization systems that do not require standard technology copper seed layers for deposition of copper gapfill. There is also a need for metallization processes that avoid the problems associated with oxide formation on the barrier materials.